This checkpoint will be seen when the WMAC has issued an error interrupt. This typically indicates some sort of hardware error. In the field, we have typically seen the following conditions trigger this error:
1. Excessively high bit error rate that the ASIC chip cannot tolerate.
2. A condition on the clock signal board that causes a register to left – shift a sequence number. (This is in the PHY – MAC interface for received data).
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