Check Point Error 90
The check point error 90 will be monitored in the BSU event logs, If the Syslog server is configured in the BSU and in the SU and If the events logs are not able to send the syslog server, then this type of Check point errors will appears in the BSU event logs.
“ Chkpt error 90 error can’t sent to Syslog Server”
Radio Control Error
From BSU fault log it is observed that "Radio control error". This issue can be any one of the followings:
1. Cable between IDU and ODU
2. Bad Radio
3. IDU port
Check the followings:
1. Verify RG-6 cable and Control is OK.
2. Connect a tested ODU with the IDU ports and see if Radio is detected or operational.
3. If possible, connect these ODUs to tested IDU (PW760 or PW1000) and see if Radio is detected or operational.
Checkpoint Error 150
1. Cable issue between WSS and Radio
2. DC Voltage approx 10-18 Volt at Radio from WSS port.
3. Internal communication between MSS- WSS.
4. Traffic on BS Ethernet port and each WSS ports at the time of error occurred
Checkpoint Error 43
If the frame started out of sync, the most likely cause of this error would be an issue with the frame sync cable (BNC connector fail - not proper crimped, short-circuit or cable break itself) then it’s indicates message Checkpoint 43 (ChkPt 43). Or if the BSU got rebooted the message can be monitored from EMS or Syslog server.
Checkpoint Error 89
This is caused by drifting of the synthesizers, and detectors re-correcting for this. No need for alarm if an isolated occurrence and the synthesizer come back into lock. If the synthesizer2 stays out of lock, it means that the radio is very likely transmitting out of the configured channel and the software will shut down WMAC so as not to cause interference.
Check Point Error 98
This checkpoint will be seen when the WMAC has issued an error interrupt. This typically indicates some sort of hardware error. In the field, we have typically seen the following conditions trigger this error:
1. Excessively high bit error rate that the ASIC chip cannot tolerate.
2. A condition on the clock signal board that causes a register to left – shift a sequence number. (This is in the PHY – MAC interface for received data).
Subscribe to:
Posts (Atom)